1. Field of the Invention
The present invention relates to a memory control circuit, especially to a circuit and its related method of controlling a data reading process of a memory module.
2. Description of Related Art
Please refer to FIG. 1, which illustrates a system structure of a conventional double data rate synchronous dynamic random access memory (DDR SDRAM). The DDR SDRAM 10 includes a memory control circuit 110 and a memory module 120. The memory control circuit 110 transmits a clock CLK to the memory module 120. The memory module 120 uses the clock CLK as a reference clock during operation. During a reading process, the memory control circuit 110 transmits a read command CMD to the memory module 120, and the memory module 120 accesses its internal data according to the read command CMD to generate a data signal DQ. The memory module 120 then transmits the data signal DQ along with a data strobe signal DQS, which is utilized to recover the data signal DQ, to the memory control circuit 110.
Please refer to FIG. 2, which illustrates a timing diagram of signals of the conventional DDR SDRAM. The data strobe signal DQS includes a preamble part tRPRE followed by a periodic clock part for sampling the data signal DQ. The length of the preamble part tRPRE is about one period of the clock CLK and the central point of the preamble part is marked as P. One purpose of the preamble part tRPRE is to indicate the starting point of the periodic clock part of the data strobe signal DQS. The preamble part tRPRE of the data strobe signal DQS must be found before the data recovery process to ensure that the data recovery process is correct. In addition, the data strobe signal DQS also includes an unstable part TRI (illustrated in stripes), during which signals hop irregularly between high level and low level.
The memory control circuit 110 samples the data signal DQ by the data strobe signal DQS to recover data. However, the clock DDR_CLK inside the memory module 120 has a certain delay with respect to the clock CLK of the memory control circuit 110 due to the wirings on the circuit board and more or less signal delays inside each component. Since the clock DDR_CLK and the clock CLK are not in phase anymore, the data strobe signal DQS generated by the memory module 120 and the clock CLK of the memory control circuit 110 do not belong to the same clock domain; therefore there must be a certain mechanism to correctly find the preamble part tRPRE of the data strobe signal DQS in situations like this.
In a conventional method, a read leveling technology is utilized to find the preamble part tRPRE of the data strobe signal DQS. The memory control circuit 110 refers to the clock CLK to generate a DQS enabling signal DQS_En, which indicates the preamble part tRPRE of the data strobe signal DQS, and therefore it would be better if the DQS enabling signal DQS_En enables (e.g., from low level to high level) at the middle point P of the preamble part tRPRE of the data strobe signal DQS. When the DQS enabling signal DQS_En enables, it means that the preamble part tRPRE of the data strobe signal DQS already occurs, implying that the process of restoring the data signal DQ is about to start. During the read leveling process, the memory control circuit 110 consecutively sends out read command CMD. Each time the read command CMD is sent, the enabling time of the DQS enabling signal DQS_En is delayed by half the period of the clock CLK, and the data strobe signal DQS is sampled by the delayed DQS enabling signal DQS_En. The DQS enabling signal DQS_En corresponding to the first read command CMD sent out by the memory control circuit 110 is determined to be the DQS enabling signal DQS_En required by the system when consecutive sampling results comply with predetermined data types. The enabling time of the DQS enabling signal DQS_En indicates the position of the tRPRE of the data strobe signal DQS. However, this method consumes lots of time and the unstable part TRI of the data strobe signal DQS probably causes this method to misjudge.
In another conventional method, the time of the preamble part tRPRE of the data strobe signal DQS is estimated by a read latency technology. The time after the memory module 120 receives the read command CMD and before it sends out the data strobe signal DQS can be estimated, such as 5 times the period of the clock CLK. Unfortunately, because there exists a delay between clock DDR_CLK and the clock CLK and the delay time is subject to the design, the manufacturing process and even the operating temperature of the circuits and the components, this method probably encounters errors when the memory control circuit 110 assumes that the preamble part tRPRE of the data strobe signal DQS is coming in 5 periods of its own clock CLK after sending out the read command CMD. In addition, the data signal DQ has to be taken into consideration in this method, which increases the operating complexity.